In forming bipolar integrated circuits, the goals include high yield, high reliability, small size, and low manufacturing costs. Existing methods of fabricating bipolar integrated circuits frequently involve steps which cause the upper surface of the circuit to be substantially non-planar. As a result, efforts at stacking integrated circuit components vertically result in a greater number of discontinuities and faults. Thus, it is desirable for stacking purposes to manufacture circuits having substantially planar upper surfaces. Such a feature would improve yield and reduce the cost of fabricating such circuits.
In making smaller circuits, the contacts for the circuit components, such as the base, collector, and emitter contacts of a transistor, become more difficult to accurately align. Limits on the tolerance of the alignment equipment make alignment difficult.
Existing methods of fabricating bipolar integrated circuits use a number of masking steps to define each region of the circuit element as well as the contact areas for each contact of the element. Each additional masking step creates a further opportunity for reducing yield and reliability and further increases the cost of fabricating the circuits.
Finally, it is desirable to fabricate bipolar transistors having relatively low collector-substrate junction capacitances, low collector, base, and emitter resistances, low emitter sidewall capacitances, and improved speed.